1. Field of the Invention
The invention relates in general to the method of fabricating a semiconductor device, and more particularly to the method of fabricating a self-align-contact with low resistance.
2. Description of the Related Art
In the semiconductor process there are many methods of fabricating a self-align-contact. One of conventional methods of forming a self-align-contact includes first providing a substrate on which there are at least two MOS devices and then forming an insulating layer, such as silicon oxide, on the two MOS devices. Each of the two MOS devices includes a polysilicon gate and spacers on the sidewalls of the gate. The two MOS devices have a common source/drain region located between the gates of the two MOS devices. The insulating layer is patterned to form a contact opening to expose the common source/drain region. A conductive layer is deposited in the self-align-contact opening to form a self-align-contact.
A process flow showing the formation of a conventional self-align-contact is illustrated by FIG. 1A-1D. Referring to FIG. 1A, a gate 102 and source/drain regions 110 are formed on a semiconductor substrate 100. The gate 102 includes a gate oxide 104, a doped polysilicon layer 106 and a cap layer 108. The cap layer 108 is formed on the doped polysilicon layer 106 to protect the doped polysilicon layer 106. A spacer 112 is formed on the sidewalls of the gate 102. The source/drain regions 110 are lightly doped drain (LDD) structures. The method of forming the source/drain regions 110 includes lightly implanting ions to the semiconductor substrate 100 using the gate 102 as a mask and heavily implanting ions to the semiconductor substrate 100 using the spacer 112 as a mask. Referring to FIG. 1B, a dielectric layer 114 is formed on the semiconductor substrate 100 by CVD.
Next, referring to FIG. 1C, the dielectric layer 114 is patterned by both a lithography process and etching to form a contact opening 117 located between two gates 102. This exposes the source/drain region 110.
Next, referring to FIG. 1D, a conductive layer 118, such as doped polysilicon, is formed in the contact opening 117 and on the semiconductor substrate 100 by deposition. The conductive layer 118 is patterned. A self-align-contact according to prior art is accomplished.
However, the above conventional method of forming a self-align-contact includes many drawbacks. Referring to FIG. 2, the width d of the spacer 112 is about 0.1 .mu.m for forming the source/drain region 110 that is a lightly doped drain (LDD) structure. When the integration of semiconductor devices increases, the space s between two gates 102 shrinks to 0.3 .mu.m or less. Therefore, the exposed area of the source/drain regions 110 decreases. When anisotropic etching is performed to form the spacer 112, the space between two gates 102 is sometimes too small to form the spacer 112. If the relation between d and s is 2d.gtoreq.s, the situation is even worse than not having any exposed remainder of the source/drain regions 110 because the adjacent spacers connect. The result of this is device failure due to the inability of the self-align-contact to form successfully.